1. Field of the Invention
This invention relates to the field of output buffers, and particularly to output buffers used to drive terminated signal lines.
2. Description of the Related Art
There are many applications in which output buffers drive respective signal lines to convey data to one or more devices connected to the signal lines. In such applications, it is important that the integrity of the data on the signal lines be maintained, so that it can be accurately detected by the receiving devices.
One such application is a random access memory (RAM) system. Dual-Inline Memory Modules (DIMMs) are the industry-standard platform on which RAM is provided for digital computers. Each DIMM is a printed-circuit board which contains a number of individual RAM integrated circuits (ICs) or “chips.” DIMMs typically contain address and/or control registers which distribute data bits to each of the DIMM's RAM chips via signal lines driven by respective output buffers.
A typical DIMM arrangement is shown in FIG. 1a. An output buffer 10 includes a drive circuit 12 which drives a signal line 14. The DIMM includes a number of RAM chips 16; dynamic RAM (DRAM) chips are shown in FIG. 1, though a DIMM can include other RAM types as well. Signal line 14 is routed to an address or control input on each RAM chip.
DIMMs are provided in a variety of configurations. Each DIMM type has an associated set of specifications, promulgated by the industry-supported JEDEC Solid State Technology Association international standards body, which govern the DIMM's configuration and operation. For some DIMM types, the specifications require that each signal line be “terminated”; i.e., that a termination resistor Rt be connected between each signal line and a fixed voltage, denoted in FIG. 1 as V+. Termination resistors serve to improve the signal quality on transmission lines such as signal line 14.
The use of termination resistors in this way can have an undesirable side effect, however, in that they tend to increase the DIMM's power consumption. For example, assuming that the output impedance of drive circuit 12 is ˜0 Ω, V+ is 0.75 volts, and Rt is 30 Ω, then the static power dissipation Pdiss associated with one signal line is:    Pdiss=(V+)2/Rt=18.75 mW/signal line. There are typically 20-30 signal lines on a DIMM, such that power dissipation due to Rt can be 500 mW or more.
One approach which has been suggested to reduce Pdiss is to make the output of drive circuit 12 a ‘tri-state’ output, which presents a high impedance to signal line 14 during a low power or ‘standby’ mode. This reduces the voltage across Rt to zero, and thus Pdiss is also reduced to zero. However, this solution may give rise to another problem, which is illustrated in FIGS. 1b and 1c. Signals provided to a DRAM input are typically received by a line receiver 20, which determines the logic state of the signal line by comparing the signal line voltage (VD) with a reference voltage (Vref). As shown in FIG. 1c, the power consumed by line receiver 20 is greatest when VD is equal to Vref, and decreases as the difference between VD and Vref increases. Vref is typically made equal to one-half of the memory system's supply voltage, which is also a preferred voltage for V+. When Vref=V+, enabling the ‘standby’ mode causes VD to be pulled up to Vref via termination resistor Rt. This causes the power consumption of each DRAM line receiver to spike, resulting in a total power consumption which may be unacceptably high.